RISC-jeV
A simulated RISC-V CPU uses Boolean lookup tables supplied by Jev.
A simulated RISC-V CPU uses Boolean lookup tables supplied by Jev.
Jev classifies Boolean gate/input combinations as Choice answers of `false` or `true`. The project turns those answers into cached gate lookup tables and uses them while simulating a SERV RISC-V CPU; cached runs make no new Jev calls, and a fresh run can replace the tables.
What is the Boolean output of AB,00? Input order: AB. Inputs: A=0, B=0.
A shared fixed state explains single-bit Boolean expressions and input ordering. The representative question is the AND gate with inputs A=0 and B=0.
Code enumerates each supported gate and bit-input combination into a bounded set of questions.
Jev chooses false or true for each requested gate case.
Responses are validated and saved as reusable gate tables; a fresh run requests replacement answers.
The simulator executes the compiled CPU with the cached tables and reports output and halt events.
It composes many tiny typed classifications into reusable lookup tables that drive a CPU simulator, making a striking example of decisions embedded in deterministic computation.